This invention relates generally to circuits utilizing silicon technology and more particularly to the nature of electrical contacts as used with this technology.
Metal silicides have found widespread use in the microelectronics industry. When formed on the surface of a transistor, for example, the silicide allows better electrical contact between the underlying silicon structure of the transistor and the metal signal and power lines used with the transistor. Metal silicide also lowers the resistivity of the silicon regions on which it is formed. These properties of silicide allow transistor devices and other silicon structures to operate at higher speeds.
The self-aligned silicide process, commonly referred to as the salicide process, is an attractive method of forming silicide on a transistor. The steps of this prior art process are illustrated in FIGS. 1A-1D.
Referring to FIG. 1A, a transistor's structure 10 is first formed using techniques well-known in the art of semiconductor device processing. As can be seen, transistor device 10 has a non-planar structure with different regions of the device being located at different levels. Typically, not all surfaces of the device are parallel to the surface of a substrate 12, upon which the device is formed. Typically, such devices include oxide spacers 14 on either side of a polysilicon surface 16 lying over a gate region 17 of the device. Under certain conditions, silicon dioxide spacers 14 will not react in the salicide process to form silicide.
Referring now to FIG. 1B, the salicide process includes the deposition of a metal layer 18. In FIG. 1C, a rapid thermal processing step (heat 19 being shown) is then completed, in which a metal silicide 20 is formed on the planar surfaces of transistor structure 10. In FIG. 1D, a selective etch is performed to remove unreacted metal from the planar and non-planar surfaces, leaving metal silicide 20 over the source/drain regions and over the gate interconnect regions of the transistor structure.
It is known that silicon dioxide does not react well in silicide formation. In general, a native silicon dioxide layer will exist upon the silicon surfaces of a silicon structure, such as that depicted in FIG. 1, and will lie between the silicon and the metal deposited to form silicide. The native silicon dioxide layer inhibits the formation of silicide and since the silicon dioxide layer is generally of an uneven thickness, the degree of inhibition of silicide formation will vary across the silicon substrate being processed. This leads to silicide that is rough and non-uniform, resulting in a device resistivity that will vary from point to point, creating non-uniformities within the device itself as well as within batches of devices that are fabricated. Excessively thin silicide may in some regions cause device failure while in other instances thinness or thickness of the silicide can cause problems during photolithographic steps as light may not be specularly reflected as appropriate.
It is known to reduce this non-uniformity by using ion implantation normal to the silicon. The implantation disrupts the silicon dioxide layer and allows more uniform silicide formation. Such a method, however, has not proven suitable in cases where non-planar surfaces exist on a silicon structure. The need thus exists for a method of forming improved contact layers on silicon structures that have not only have a native silicon dioxide layer on contact surfaces but also have non-planar surfaces.